Cache memory having flags for inhibiting rewrite of replacement

Details Cache memory having flags for inhibiting rewrite of replacement Cache memory having flags for inhibiting rewrite of replacement

1998-05-27

2000-11-07

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, 711133, 711159, 714 42, G06F 1200

Patent

active

061450553

ABSTRACT:
When a fault cell is found in an initial state at the time of power-on, LRU bit is rewritten so that the LRU bit does not take an entry corresponding to a fault cell as an object of updating and then a LRU write inhibit flag is set to inhibit a write in the fault cell. If a fault cell is found during operation, a valid bit corresponding to an entry corresponding to the fault cell is rewritten to invalid condition. Then the LRU bit is rewritten so that the LRU bit does not take an entry corresponding to the fault cell as an object of updating and then a LRU write inhibit flag is set to inhibit a write in the fault cell.

REFERENCES:
patent: 5019971 (1991-05-01), Lefsky et al.
patent: 5070502 (1991-12-01), Supnik
patent: 5805606 (1998-09-01), Robertson et al.
patent: 5835504 (1998-11-01), Balkin et al.
patent: 5926484 (1999-07-01), Takusagawa

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