Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1995-02-27
1998-09-01
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711128, 711133, 711141, 711168, 36518904, 365 49, G06F 1200
Patent
active
058025863
ABSTRACT:
A multiple-way, set associative cache memory (20) allows burst read and burst write operations to occur simultaneously on different columns within a memory block during a read-modify-write operation. This is accomplished by using a write column logic (47) and a read column logic (51) to delay write column decode signals by one clock cycle from the read column decode signals. When data is being burst into and out of the cache during the read-modify-write operation, the first read cycle from the cache array (40) occurs, and one clock cycle later, the first write cycle occurs. The first write cycle occurs during the same time interval as the second read cycle. This increases the speed of a read-modify-write operation, relaxes timing constraints on the read and write operations, while reducing the power consumption of the cache.
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Bader Mark D.
Jones Kenneth W.
Kahlich Arthur D.
Chan Eddie P.
Hill Daniel D.
Kim Hong C.
Motorola Inc.
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