Cache memory having a DRAM memory cell

Details Cache memory having a DRAM memory cell Cache memory having a DRAM memory cell

1999-10-19

2002-08-27

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06442742

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a cache memory having a DRAM memory cell and, more particularly, to a semiconductor memory device having therein a micro processing unit and a cache memory having a DRAM memory cell array.
(b) Description of the Related Art
In view of a low operational speed of a main storage device used for a micro processing unit (MPU) in a computer system, it is usual that the MPU is associated with a cache memory having a higher operational speed. The cache memory temporarily stores some of data for the MPU to compensate the low speed of the main storage device.
In general, the cache memories, required to have a higher operational speed, have been implemented by static random access memories (SRAMs), which generally have a larger circuit scale however. Thus, a small-capacity SRAM is generally used heretofore for the cache memory.
It is desirable that a dynamic random access memory (DRAM) having a larger storage capacity be used as the cache memory for reducing the chip size of the LSI. If the cache memory is to be implemented by a DRAM, a configuration may be employed in that the MPU and bonding pads are disposed in the central area and the peripheral area, respectively, of a semiconductor chip, with the DRAM cache memory disposed between the MPU and the bonding pads. If the DRAM has a redundancy function wherein a defective row of memory cells are replaced by a redundancy row of memory cells, a large number of redundancy fuses are disposed in the DRAM for informing the defective row to effect the redundancy function.
If the configuration as described above is employed in the semiconductor integrated circuit, the large number of redundancy fuses are inevitably disposed between the MPU and the bonding pads. This may cause complicated routes for the signal lines or interconnects connecting the MPU with the bonding pads due to the interference between the signal lines and the redundancy fuses. Thus, it is desired to design a semiconductor integrated circuit having a MPU and a cache memory implemented by a DRAM to have a simple structure for the arrangement of the signal lines.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a semiconductor integrated circuit including a MPU and a cache memory and having a simple structure for the arrangement of the signal lines.
The present invention provides a semiconductor integrated circuit including a microprocessor unit (MPU), a cache memory for temporary storing data for the MPU, and a plurality of signal lines for connecting the MPU with bonding pads, the cache memory including at least one DRAM block disposed between the MPU and the bonding pads, the DRAM block having a plurality of rectangular fuse blocks each including a plurality of elongate redundancy fuses for storing data for a redundancy function of the DRAM block, the rectangular fuse blocks having a pair of elongate sides extending substantially parallel to the signal lines.
In accordance with the semiconductor integrated circuit of the present invention, the configuration of the fuse blocks provides a larger space for the signal lines, thereby reducing overall chip size of the semiconductor integrated circuit.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.


REFERENCES:
patent: 4678889 (1987-07-01), Yamanaka
patent: 5822603 (1998-10-01), Hansen et al.
patent: 6018488 (2000-01-01), Mishima et al.

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