Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-07-12
2005-07-12
Anderson, Matthew D. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000
Reexamination Certificate
active
06918011
ABSTRACT:
Information specifying invalidating areas of a main memory is stored in an area specifying register. Each time a signal indicating an index address is input to a tag memory and a data memory, cached data of the index address of a data memory is output, a tag address is output from a tag memory. A combined address of the tag address and the index address indicates an address of the main memory from which data is written at the index address of the data memory. Thereafter, it is judged whether or not an area of each combined address of the main memory agrees with one of the invalidating areas. In case of the agreement of the area of each combined address and one invalidating area, the invalidating processing is performed for the cached data of the index address corresponding to the combined address.
REFERENCES:
patent: 5860110 (1999-01-01), Fukui et al.
patent: 2001-134490 (2001-05-01), None
“Section 4 Caches”, SuperH™(SH)32-Bit RISC MCU/MPU Series, SH7751, High Performance RISC Engine, Hardware Manual (ADE-602-201, Rev. 1.0), Hitachi, Ltd., Apr. 10, 2000, pp. 61-81.
“Chapter 5 Caches and Write Buffer”, ARM 1022E™ Technical Reference Manual (ARM DDI 0237A), ARM Limited., 2001, pp. 5.1-5.18.
Anderson Matthew D.
Burns Doane , Swecker, Mathis LLP
Renesas Technology Corp.
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