Cache memory exchange optimized memory organization for a comput

Details Cache memory exchange optimized memory organization for a comput Cache memory exchange optimized memory organization for a comput

1998-03-12

2000-09-26

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711121, 711133, 711148, 711153, 710132, G06F 1208

Patent

active

061254290

ABSTRACT:
Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping "fill" requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the "victim" data in that CPUs cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the `ships crossing in the night` problem is avoided.

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