Cache memory employing dynamically controlled data array start t

Details Cache memory employing dynamically controlled data array start t Cache memory employing dynamically controlled data array start t

1996-05-24

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

395559, G06F 1206

Patent

active

058601279

ABSTRACT:
A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

REFERENCES:
patent: 4502110 (1985-02-01), Saito
patent: 4803616 (1989-02-01), Uchiyama et al.
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5018061 (1991-05-01), Kishigami et al.
"Cache Memories" by Alan Jay Smith, Computing Surveys, vol. 14, No. 3, (1982) pp. 473-530.
"Computer Organization & Design--The Hardware/Software Interface" Morgan Kaufmann Publishers, (1994) pp. 454-527.
Nikkei Electronics, Feb. 14, 1994, pp. 79-92.
Nikkei Electronics, Mar. 27, 1995 pp. 13-20.

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