Cache memory device of DRAM configuration without refresh functi

Details Cache memory device of DRAM configuration without refresh functi Cache memory device of DRAM configuration without refresh functi

1997-01-17

1998-09-01

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Differential sensing

365210, 365222, G11C 702, G11C 700

Patent

active

058020020

ABSTRACT:
In a cache memory device including a DRAM cell array, a DRAM cell circuit is connected to word lines. A sense amplifier and a write amplifier are provided to the DRAM cell circuit for writing a certain data signal into one of memory cells connected to a selected word line. A read amplifier as well as the sense amplifier is provided to read data from one of the memory cells to generate a validity signal for showing whether data of the DRAM cell array is valid or invalid.

REFERENCES:
patent: 5421000 (1995-05-01), Fortino et al.
patent: 5577223 (1996-11-01), Tanoi et al.
Cortadella et al., "Dynamic RAM For On-Chip Instruction Caches", Computer Architecture News, vol. 16(4): 45-50, (1988), no month.

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