Cache memory device

Details Cache memory device Cache memory device

1994-09-09

2001-08-07

Myers, Paul R. (Department: 2181)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

06272592

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the technological field of buffer or cache memories.
It finds a general application in data processing systems.
2. Background Information
Technological progress, in particular in the field of clock speeds and the integration of processors, tends to reduce increasingly the cycle times of the said processors and to permit the sequencing and execution of several instructions per cycle.
It follows therefrom that there is an increasingly heavy demand on the data flow in the main memory of a data processing system.
However, the technological progress has not made it possible to reduce the time of access to the data in the main memory at the same rate as the cycle times of the processors.
Indeed at present, the access time in the main memory is often of the order of several tens of processing cycles, even hundreds of processing cycles.
One known solution for masking the latency of the access to the data in the main memory lies in using cache memories (Computing Surveys, Vol.14, No.3, September 1982, pages 473-530, “Cache Memories”).
In general, a cache memory is a fast access memory, generally of a small size, wherein a part of the set of data stored in the main memory is stored.
In practice, when a processor makes a request comprising a main address in the main memory, and possibly data, the cache memory responds to the said request either by connecting the main address contained in this request and a data line of the cache memory, when the desired data item is present and valid in the cache memory, or by signalling that it is absent in the opposite case. In this latter case, the processor addresses the main memory for accessing the desired data item. The data line in the main memory containing the desired data item can then be loaded into the cache memory.
Several cache memory systems are known, in particular the direct recording system also called “direct mapped”, the wholly associative multibank system and the associative multibank set system (EP-A-0 334 479). These systems will be described in greater detail below.
It is clear that the use of cache memories accelerates the time of access to the data in the main memory, thanks to the fact in particular that the cache memories are faster than the main memories.
Nevertheless, the effective performance of data processing systems using cache memories depends on the average hit rate during access to the data in the said cache memories.
Now, this average hit rate is not entirely satisfactory in the above mentioned systems of cache memories.
SUMMARY OF THE INVENTION
The object of the invention is precisely that of improving the average hit rate during access to the data in the cache memories.
The invention relates to a cache memory device using a multibank system.
In the known way, the cache memory device comprises:
at least one request input/output for receiving a request for access to a data item stored in the addressable main memory or in another addressable cache memory, comprising a main address, and possibly data;
at least one main memory input/output connected to the main addressable memory for accessing the said desired data item of the main memory;
a plurality of memory banks, each having a number of lines capable of containing data, these lines being capable of being individually designated by a local address in each bank;
computing means connected to the request input/output and capable of answering the request by connecting the main address contained in this request to a local internal address in each of the banks, the line thus designated in the bank being the only line of the said bank that is capable of containing the data labelled by the main address;
loading means connected to the main memory input/output for loading the data line of the main memory containing the desired data item into the cache memory when it is not present in the cache memory.
According to a general definition of the invention, the computing means establish the said relation between the main address and the local address in the bank in accordance with a predetermined law associated with the said bank; at least two of the predetermined laws are distinct according to the banks in question; and the two banks in question are addressed separately, according to their respective law.


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