Cache memory controlled by system address properties

Details Cache memory controlled by system address properties Cache memory controlled by system address properties

2000-10-31

2003-09-30

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S001000, C711S118000, C711S130000, C711S144000, C711S147000, C711S209000

Reexamination Certificate

active

06629187

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to microprocessors, and more specifically to improvements in cache memory access circuits, systems, and methods of making.
BACKGROUND OF THE INVENTION
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile telecommunication processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets.
Cache memory is provided in order to reduce memory access time for instructions and/or data and thereby provided higher instruction throughput. In a computer system that uses cache memory, certain cache memory modes need to be controlled. Often the signals to control the cache memory in a general microprocessor system come from a memory management unit. However, in embedded system such as those that employ digital signal processors, there is often no memory management unit.
In addition, various memory mapped peripheral devices that may be included in a particular embedded system may not all have the same access capabilities.
SUMMARY OF THE INVENTION
In general, and in a form of the present invention, a digital system is provided with a microprocessor, a cache and various memory and devices. Signals to control certain cache memory modes are provided by a physical address attribute memory (PAAM). For devices present in the address space of the digital system that have different capabilities and characteristics, misuse is prevented by signaling an error or otherwise limiting the use of each device in response to attribute bits in the PAAM associated with the memory mapped address of the device. A memory management unit with address translation capabilities and/or memory protection features may also be present, but is not required for operation of the PAAM.


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