Cache memory control method and cache memory control device

Details Cache memory control method and cache memory control device Cache memory control method and cache memory control device

2006-03-22

2009-12-22

Patel, Hetul (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S133000, C711S144000

Reexamination Certificate

active

07636812

ABSTRACT:
An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for setting whether a cache refill to each way in the cache memory is allowed for each CPU or each thread, first, a first cache hit/miss determination is performed only on the way for which a refill is set to be allowed (Steps2-1and2-2), and if the first cache hit/miss determination results in a cache hit, the access is ended (Step2-6). In the case of a cache miss, the way for which a refill is not set to be allowed is accessed (Step2-3), or a second hit/miss determination is performed by accessing all the ways (Step2-4).

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