Cache memory control method and apparatus, and method and appara

Details Cache memory control method and apparatus, and method and appara Cache memory control method and apparatus, and method and appara

1996-09-16

1998-06-02

Swann, Tod R.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711118, 711127, 711157, 711173, 711122, 711 3, G06F 1300, G06F 1200

Patent

active

057616957

ABSTRACT:
In a memory control apparatus which has a main memory constructed by a plurality of memory areas and a cache memory which can be accessed at a speed higher than that of the main memory and in which the main memory or the cache memory is accessed in response to a memory access request from an access request side and data is read out and transferred to the access request side, an accessing speed of every plurality of memory areas in the main memory is identified and an area that is cachable for the cache memory among the plurality of memory areas in the main memory is set in accordance with the identified accessing speed of every plurality of memory areas in the main memory. In a memory control apparatus for performing an interleave access or a non-interleave access to an information memory medium having a plurality of banks of different capacities, a boundary address indicative of a boundary between the interleave access area and the non-interleave access area is compared with an access address to the information memory medium, and on the basis of the comparison result, the interleave access or non-interleave access is executed to the information memory medium.

REFERENCES:
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patent: 5469555 (1995-11-01), Ghosh et al.
patent: 5539898 (1996-07-01), Trevett et al.
patent: 5574939 (1996-11-01), Keckler et al.

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