Cache memory control device for multi-processor system

Details Cache memory control device for multi-processor system Cache memory control device for multi-processor system

2001-05-25

2003-06-10

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C710S056000

Reexamination Certificate

active

06578112

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a cache memory control device and, more particularly, to a cache control system usable with advantage for command pre-fetch in a multi-processor system.
BACKGROUND OF THE INVENTION
FIG. 11
shows an exemplary structure of a conventional communication LSI and more specifically a structure of a single PHY (physical layer) LSI of ADSL (Asymmetrical Digital Subscriber Line) modem. This ADSL is a high-speed digital transmission system in which the speed from a subscriber accommodating station of a communication undertaker to user's premises (downstream) is asymmetrical with respect to that from the user's premises to the accommodating station (upstream) and which uses a pre-existing telephone cable. A signal processor
8
which is adapted for performing digital signal processing on a communication LSI
200
C, a baseband unit
9
and an ATM (asynchronous transfer mode) TC (transmission convergence)
10
make up a communication system hardware. The signal processor
8
includes an interfacing circuit
6
made up of a driver receiver circuit of a line (line), a converting circuit
7
, made up of a digital-analog converting circuit (D-A)
7
-
1
for digital-analog converting transmission signals, and an analog-digital converting circuit (A-D)
7
-
2
for analog-digital converting transmission signals. The communication LSI
200
C also includes a processor (CPU)
2
, a work RAM
3
, an instruction RAM
5
made up of plural RAM banks (eight banks in
FIG. 11
) in which commands to be executed in the processor
2
are pre-fetched and stored, and an instruction RAM controller
1
C. The processor
2
is connected over an internal bus
4
to the communication system hardware, such as work RAM
3
, instruction RAM controller
1
C and the signal processor
8
etc. The ATM TC (transmission convergence)
10
exchange data with e.g., an upper layer of the PHY (physical layer) supported by the communication LSI
200
C.
An external instruction ROM (read-only memory)
12
, having an instruction data queue (instructions (commands) and data for executing communication control in the processor
2
) stored therein, is externally mounted to the LSI
200
C. The instruction RAM controller IC (cache controller) pre-fetches instruction data from the external instruction ROM
12
for storage in a relevant bank in the instruction RAM
5
.
The instruction RAM controller IC includes a command register
11
C for pre-fetch, as a control register. Even if there is no cache error, the processor
2
writes a pre-fetch request command in the command register
11
C at an arbitrary time point to update the instruction RAM
5
.
In this command register
11
C, start addresses of instruction data, pre-fetched from the instruction RAM
12
, and bank numbers of the instruction RAM
5
, in which to load the pre-fetched instruction data, are set, and instruction data read out from a relevant address are written in a relevant bank in the instruction RAM
5
in an amount corresponding to the bank memory capacity.
With the instruction RAM
5
being made up of plural banks, the contents of a given bank of a given one of the instruction RAMs
5
can be updated during the accessing of another bank to render queuing of cache updating processing unnecessary to improve the processing performance.
Meanwhile, as to a cache memory system in which the cache memory is made up of plural banks, a cache controller is provided with a command register, and a cache update command is set in the command register under a command from the processor to enable loading (pre-fetch) command to the cache memory at an arbitrary time even if there has occurred no cache error, reference may be had e.g., to the JP Patent Kokai JP-A-11-143775.
Since plural pre-fetch requests are not superposed in this configuration of the signal PHY type LSI
200
C, there is provided no function for determining the priority sequence of the pre-fetch requests.
FIG. 12
shows the configuration of a multi-PHY type LSI
200
D, in which plural single (sole line) PHY type LSI
200
Cs, shown in
FIG. 11
, are used to allow to cope with plural lines.
Referring to
FIG. 12
, circuit blocks
100
1
to
100
4
are provided for each PHY. Each of the circuit blocks
100
1
to
100
4
includes communication hardware comprised of a CPU
2
, an instruction RAM controller
1
C, an instruction RAM
5
, a signal processor
8
and a baseband processor
9
.
Referring to
FIG. 12
, since no measures are taken to enable the co-owning of the external instruction ROM, four external instructions ROMs
12
are each externally connected to each of PHYs of the LSI
200
Ds adapted to cope with four lines. The LSI
200
is in need of a number of terminals corresponding to the number of terminals of these four instructions ROMs. For example, if an address signal is of a 20-bit width and the data is of 8-bit width,
112
terminals are required in order to cope with four instruction ROMs. The number of the terminals is increased further if control signals such as chip enable signals etc. are taken into consideration.
SUMMARY OF THE DISCLOSURE
The conventional multi-processor system for coping with plural lines, as described above, has a drawback that a number of external ROM interfaces corresponding to the number of lines (PHYs) to be supported, are required, thus increasing the number of the LSI external terminals by multi-physical layering, termed as “multi-PHYing” herein.
In particular, the program stored in the instruction ROM is increased in size, as the communication control is becoming complex and as control function is diversified, thus increasing the memory capacity of the instruction ROM. In keeping up therewith, the number of address signals of the instruction ROM is increased. Under this situation, the configuration shown in
FIG. 12
leads directly to an increased number of LSI pins.
Moreover, since plural external instruction ROMs are required in association with the number of lines, it offers a poor cost reducing effect per line, too.
Also, high-speed processing is required in cache memory control and in pre-fetch control, such that deterioration in the control performance reflects itself readily in the processing performance of the processor. Thus, in case where, in the communication circuit in need of high-speed processing, a configuration is employed such that the instruction ROM is co-owned by the respective PHYs, measures for suppressing the lowering of the processing performance are necessitated.
It is therefore an object of the present invention to provide a cache memory control device in which an external instruction ROM, having stored therein program commands for loading in the cache memory, can be co-owned by plural processors, and in which the lowering of the pro performance of the processor can be suppressed to a minimum.
It is another object of the present invention to provide a cache memory control device in which the number of external terminals of the LSI having plural processors can be reduced. Other objects, features and advantages of the present invention will become apparent from the following description of preferred embodiments and the claims.
According to a first aspect of the present invention, there is provided a novel cache memory control device for a multi-processor system having a plurality of processors. The cache memory control device comprises a plurality of cache memories provided in association with a plurality of the processors, respectively; a memory device co-owned by a plurality of the cache memories having stored therein instruction data to be stored in each of the cache memories; and a plurality of command registers associated with the cache memories for controlling updating of the cache memories in association with respective ones of the plural cache memories. Each of the cache memories stores therein instruction data pre-read from the memory device, and the instruction data is used in the processor corresponding to each of the cache memories. Each of the processors associated with each of the cach

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