Cache memory control apparatus utilizing a bit as a second valid

Details Cache memory control apparatus utilizing a bit as a second valid Cache memory control apparatus utilizing a bit as a second valid

1996-04-12

1998-09-15

Asta, Frank J.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711128, 711 3, 364DIG1, G06F 1300

Patent

active

058095357

ABSTRACT:
A cache memory control apparatus for a cache memory having a data memory, includes an address array, a valid bit register, a comparator, and a dual-purpose register. The dual-purpose register stores one of a valid bit and a part of an address tag. The cache memory control apparatus applies to both a standard system with a plurality of blocks-per-line and a subordinate system with one block-per-line.

REFERENCES:
patent: 4244033 (1981-01-01), Hattori
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patent: 5367659 (1994-11-01), Iyengar et al.
patent: 5483644 (1996-01-01), Richardson
patent: 5586279 (1996-12-01), Pardo et al.
Yong. S. Lee, "A Secondary Cache Controller Design for a High-End Microprocessor", Aug. 1992, IEEE Journal of Solid-State Circuits, vol. 27(8), pp. 1141-1146.

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