Cache memory control apparatus and processor

Details Cache memory control apparatus and processor Cache memory control apparatus and processor

2005-12-27

2005-12-27

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S119000, C711S123000, C711S125000, C711S126000, C711S141000

Reexamination Certificate

active

06981103

ABSTRACT:
A cache memory control apparatus (20) that may control a cache memory (100) has been disclosed. Cache memory control apparatus (20) may include a control section (21). When a cache miss occurs, a refill request for a line (118) of data may be executed. In response to the refill request, control section (21) may perform control to make a valid bit (103) and a TAG portion (102), corresponding to line (118) of data to be refilled, invalid. This may occur while accessing the address corresponding to the cache miss from an external memory (200). In this way, if a reset occurs during the refill operation, a cache memory control apparatus (20) may recover a cache memory to a state before resetting in a reduced time period. Upon completion of the refill operation, valid bit (103) and TAG portion (102) may be updated.

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English Bibliography and Abstract of JP 05-012109 (cited above).
Japanese Patent Office Action of May 10, 2005.
English Translations of the indicated portions of the above-referenced Japanese Patent Office Action.

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