Cache memory containing extra status bits to indicate memory reg

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711141, G06F 1208

Patent

active

056665148

ABSTRACT:
The present invention provides a digital computer memory cache organization for efficient data logging, log-based copy and rollback, high-performance I/O, network switching and multi-cache consistency maintenance. The cache organization implements efficient selective cache write-back, mapping and transferring of data. Write or store operations to cache lines tagged as logged are written through to a log block builder associated with the cache. Non-logged store operations are handled local to the cache, as in a writeback cache. The log block builder combines write operations into data blocks and transfers the data blocks to a log splitter. A log splitter demultiplexes the logged data into separate streams based on address.

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