Cache memory consistency control with explicit software instruct

Details Cache memory consistency control with explicit software instruct Cache memory consistency control with explicit software instruct

1985-06-28

1987-12-15

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1208

Patent

active

047137550

ABSTRACT:
Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.

REFERENCES:
patent: 3771137 (1973-11-01), Barner et al.
patent: 3845474 (1974-10-01), Lange et al.
patent: 4156906 (1979-05-01), Ryan
IBM Technical Disclosure Bulletin, "Technique for Improved Channel Performance", by J. F. Court and K. L. Leiner, vol. 24, No. 7A, Dec. 1981, pp. 3128-3129.
IBM Technical Disclosure Bulletin, "Vary Storage Physical On/Off Line in a Non-Store-Through Cache System" by B. B. Moore et al, vol. 23, No. 7B, Dec. 1980, p. 3329.
The 11th Annual International Symposium on Computer Architecture, Jun. 5-7, 1984, Ann Arbor, Michigan, "A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories", Mark S. Papamarcos and Janak H. Patel, pp. 348-354.

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