Cache memory circuit

Details Cache memory circuit Cache memory circuit

1996-09-18

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711155, 711159, 711134, G06F 1200

Patent

active

058601023

ABSTRACT:
A cache memory circuit 36 is described which has a separate read bus 90 and write bus 98. When a given cache row is selected, then simultaneous read and write operations can take place to different words (W#0, W#1, W#2, W#3) within the cache row using the read bus and the write bus. The cache memory circuit 38 having this configuration is particularly suited for use as a write back cache. When a cache miss occurs causing the need for a cache row to be replaced, then the words are replaced starting with the word to which an attempted access triggered the cache miss and proceeding in ascending address order.

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