Cache memory cell with a pre-programmed state

Details Cache memory cell with a pre-programmed state Cache memory cell with a pre-programmed state

1997-12-02

2000-05-30

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711103, 711129, 711173, 365104, 365154, 365156, G06F 1208

Patent

active

06070229&

ABSTRACT:
A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data written into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.

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patent: 4638465 (1987-01-01), Rosini et al.
patent: 4977498 (1990-12-01), Rastegar et al.
patent: 5353248 (1994-10-01), Gupta
patent: 5584014 (1996-12-01), Nayfeh et al.
patent: 5586295 (1996-12-01), Tran
patent: 5923582 (1999-07-01), Voss

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