Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-11-03
2000-05-23
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711145, 711147, 711149, 711156, G06F 1200
Patent
active
060676019
ABSTRACT:
An apparatus employing a cache memory based approach to instruction execution includes a cache memory and one or more control units. The control units operate the cache memory to directly supply appropriate ones of a plurality of values stored in selected ones of said cache locations for a plurality of variables to one or more arithmetic logic units (ALU) as inputs to arithmetic/logic operations, and/or to directly accept and store results of arithmetic logic operations from the one or more ALU as values of the variables in selected ones of said cache locations. The direct supplying and the direct accepting and storing are performed responsive to instructions specifying said arithmetic/logic operations and logically designating the variables associated with the specified arithmetic/logic operations.
REFERENCES:
patent: 4525780 (1985-06-01), Bratt et al.
patent: 4959777 (1990-09-01), Holman, Jr.
patent: 5185878 (1993-02-01), Baror et al.
patent: 5228135 (1993-07-01), Ikumi
patent: 5287490 (1994-02-01), Sites
patent: 5404469 (1995-04-01), Chung et al.
patent: 5430862 (1995-07-01), Smith et al.
patent: 5438668 (1995-08-01), Coon et al.
patent: 5568401 (1996-10-01), Narayanaswami
patent: 5574873 (1996-11-01), Davidian
patent: 5574927 (1996-11-01), Scantlin
patent: 5701432 (1997-12-01), Wong et al.
patent: 5742802 (1998-04-01), Harter et al.
patent: 5774710 (1998-06-01), Chung
patent: 5787478 (1998-07-01), Hicks et al.
patent: 5893147 (1999-04-01), Deng
patent: 5909695 (1999-06-01), Wong et al.
patent: 5940626 (1999-08-01), Sollars
patent: 5946710 (1999-08-01), Bauman et al.
Computer Architecture and Quantitative Approach; Authors: John L. Hennessy, David A. Patterson; Morgan Kaufmann Publishers, Inc., 1990, Chapter 3, entitled "Instruction Set Design: Alternatives and Principles", pp. 89-137.
Computer Architecture and Quantitative Approach; Authors: John L. Hennessy, David A. Patterson; Morgan Kaufmann Publishers, Inc., 1990, Chapter 5, entitled "Basic Processor Implementation Techniques", pp. 199-248.
Brecis Communications
Cabeca John W.
Tzeng Fred F.
LandOfFree
Cache memory based instruction execution does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache memory based instruction execution, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory based instruction execution will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1844481