Cache memory architecture with system controller device that...

Details Cache memory architecture with system controller device that... Cache memory architecture with system controller device that...

2007-07-10

2007-07-10

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S001000, C711S003000, C711S119000, C711S150000, C711S151000, C711S152000, C711S158000, C711S168000

Reexamination Certificate

active

11426758

ABSTRACT:
A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose RAM before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides in the cache memory. The comparison may also be performed concurrently by a system controller device, which may abort the main memory access if a cache hit is detected.

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