Cache memory apparatus and computer readable recording...

Details Cache memory apparatus and computer readable recording... Cache memory apparatus and computer readable recording...

2000-03-20

2003-04-08

Iqbal, Nadeem (Department: 2785)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C711S133000

Reexamination Certificate

active

06546501

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a cache memory apparatus having a plurality of cache memories and a computer readable recording medium on which a program for controlling the cache memory is recorded thereon. More particularly, this invention relates to a cache memory apparatus being capable of avoiding system down caused by occurrence of a parity error and a computer readable recording medium on which a program for controlling the cache memory is recorded thereon.
BACKGROUND OF THE INVENTION
With popularization of personal computers, high-speed performance is further demanded. Accordingly, systems each comprising a cache memory apparatus constituted by a plurality of cache memories to achieve high-speed access are popularly used. On the other hand, since an amount of processing performed by a computer increases, emphasis is required to be given on the improvement in reliability of such systems. It is also desired that the system continues to operate without stopping the system even if a minor failure occurs.
FIG. 19
is a block diagram showing the configuration of a conventional cache memory apparatus. The cache memory apparatus shown in
FIG. 19
comprises a multiple cache memory (primary cache memory
13
and secondary cache memory
14
) to eliminate a difference in the processing speed between a CPU (Central Processing Unit)
11
and a main memory device
16
. The CPU
11
accesses the primary cache memory
13
, the secondary cache memory
14
, or the main memory device
16
to read/write data. The main memory device
16
is a hard disk drive for example. The main memory device
16
has, as characteristic features, a large capacity and an access time which is longer than that of the primary cache memory
13
or the secondary cache memory
14
. All the data that is used by the CPU
11
is stored in the main memory device
16
.
The primary cache memory
13
and the secondary cache memory
14
are SRAMs (Static Random Access Memories) for example, and has, as characteristic features, an access time which is-shorter than that of the main memory device
16
. The primary cache memory
13
also has, as characteristic features, an access time which is shorter than that of the secondary cache memory
14
. More specifically, of the primary cache memory
13
, the secondary cache memory
14
, and the main memory device
16
, the primary cache memory
13
has the shortest access time, the secondary cache memory
14
has an access time which is longer than that of the primary cache memory
13
, and the main memory device
16
has the longest access time. In addition, with respect to a memory capacity, the memory capacity of the main memory device
16
is largest, the memory capacity of the secondary cache memory
14
is second largest, and the memory capacity of the primary cache memory
13
is the smallest.
Data transmission between a CPU and a cache memory (main memory device) is generally performed in units of lines. Several methods are available which allow data on the main memory device to correspond to lines in the cache memory. As a typical method, the following set associative method is known. That is, the main memory device and the cache memory are divided into a plurality of sets (set of lines: called a way), and data on the main memory device can be placed on determined lines in the way. The set associative method including N ways is called an N-way set associative method. A method in which a cache memory is handled as one way is called a direct mapping method (or one-way set associative method).
The primary cache memory
13
stores a part of the data stored in the main memory device
16
, and is a memory using a 4-way set associative method as shown in FIG.
21
. As shown in
FIG. 21
, primary cache memory
13
is constituted by a primary tag RAM
13
a
for holding addresses A, B, C, and D or the like of data a, b, c, and d or the like, and a primary data RAM
13
b
for holding the data a, b, c, and d or the like. The primary tag RAM
13
a
and the primary data RAM
13
b
are divided into a plurality of ways to be managed. The way of the primary tag RAM
13
a
and the way of the primary data RAM
13
b
correspond to each other in a one-to-one relationship. For example, the address A held in a unit (to be referred to as an entry) constituting way
0
in the primary tag RAM
13
a
and the data a held in the entry of way
0
in the primary data RAM
13
b
correspond to each other in a one-to-one relationship.
The secondary cache memory
14
is a memory for storing part of data held in the main memory device
16
. This secondary cache memory
14
uses a direct mapping method. As shown in
FIG. 21
, the secondary cache memory
14
is constituted by a secondary tag RAM
14
a
for holding tag information consisting of an address ADR, an INCL bit, and a way WAY, and a secondary data RAM
14
b
for holding the real data. The address ADR represents the address of data held in the secondary data RAM
14
b
. The INCL bit represents whether corresponding data is held in the primary data RAM
13
b
or not. The INCL bit is “1” if the data is held in the primary data RAM
13
b
, and it is “0” if no data is held in the primary data RAM
13
b
. The way WAY represents the number of a way in the primary cache memory
13
in which the corresponding data is held.
Returning to
FIG. 19
, a primary cache access control device
12
controls access from the CPU
11
to the primary cache memory
13
, and compares the address of data to be read with an address of the primary tag RAM
13
a
according to a read request from the CPU
11
. When the addresses are equal to each other (this state is called cache hit), the primary cache access control device
12
performs control or the like to read the data corresponding to the address. On the other hand, when the addresses are not equal to each other (this state is called cache miss), the primary cache access control device
12
performs control to access the secondary cache memory
14
. A secondary cache access control device
15
controls access from the CPU
11
to the secondary cache memory
14
, and compares the address of data to be read with an address of the secondary tag RAM
14
a
. In case of cache hit, the secondary cache access control device
15
performs control or the like to read the data corresponding to the address. In case of cache miss, the secondary cache access control device
15
performs control or the like to access the main memory device
16
.
With reference to the flow chart shown in FIG.
20
and the FIG.
19
and
FIG. 21
, the operation of a conventional cache memory apparatus will be explained below. In step SA
1
shown in
FIG. 20
, the primary cache access control device
12
checks whether a read request is generated by the CPU
11
. If the check result is “No”, this check is repeated. The read request is a request that data should be read from the primary cache memory
13
, the secondary cache memory
14
or the main memory device
16
.
For example, when a read request for requesting that the data e of the address E shown in
FIG. 21
should be read is generated by the CPU
11
, the primary cache access control device
12
sets the check result in step SA
1
as “Yes”. In this manner, in step SA
2
, the primary cache access control device
12
accesses the primary cache memory
13
(r
1
in
FIG. 21
) to compare the address E with an address held in the primary tag RAM
13
a .
In step SA
3
, the primary cache access control device
12
checks whether the address E is present in the primary tag RAM
13
a
or not, i.e., whether cache hit is established or not. In this case, since the address E is not present in the primary tag RAM
13
a
, the primary cache access control device
12
determines cache miss (r
2
in
FIG. 21
) to set the check result in step SA
3
in “No”. If the check result in step SA
3
is “Yes”, in step SA
4
, the CPU
11
reads a data corresponding to the address E from the primary data RAM
13
b.
In step SA
5
, the secondary cache access control device
15
accesses the secondary

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