Cache memory and method of controlling memory

Details Cache memory and method of controlling memory Cache memory and method of controlling memory

2004-11-24

2009-12-22

Thai, Tuan V (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S133000, C711S145000

Reexamination Certificate

active

07636811

ABSTRACT:
A cacheable memory access space receives memory access addresses having different data structures according to a status of a cache capacity from a processor. A cache hit detector determines whether data has been hit based on a mode signal, an enbblk [n] signal, and a signal indicating whether the way is valid or invalid, which are preset in the cache hit detector, a tag comparison address received from the cacheable memory access space, and a tag received from the storage unit.

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Communication from the European Patent Office dated Nov. 2, 2007 for corresponding European Patent Application No. 04257449.1-1229.

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