Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-07-19
2011-07-19
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S134000, C711S136000, C711S144000, C711S154000, C711S159000, C711S160000
Reexamination Certificate
active
07984243
ABSTRACT:
A cache memory according to the present invention includes a W flag setting unit that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order and a replace unit that selects a cache entry for replacement based on the modified order data and replaces the cache entry.
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Kawai Hazuki
Miyasaka Shuji
Nakanishi Ryuta
Tanaka Tetsuya
Greenblum & Bernstein P.L.C.
Panasonic Corporation
Savla Arpan P.
Shah Sanjiv
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