Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-12-21
2008-11-18
Ellis, Kevin (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07454575
ABSTRACT:
The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.
REFERENCES:
patent: 4928239 (1990-05-01), Baum et al.
patent: 6205521 (2001-03-01), Schumann
patent: 7065613 (2006-06-01), Flake et al.
patent: 7203798 (2007-04-01), Kawamoto
patent: 0997821 (2000-05-01), None
patent: 3-054649 (1991-03-01), None
patent: 7-084879 (1995-03-01), None
patent: 8-069417 (1996-03-01), None
patent: 2000-029788 (2000-01-01), None
patent: 2000-200221 (2000-07-01), None
patent: 2001-222467 (2001-08-01), None
patent: 2003-223360 (2003-08-01), None
English language Abstract of JP 2003-223360.
English language Abstract of JP 2000-029788.
English language Abstract of JP 2001-222467.
English language Abstract of JP 3-054649.
English language Abstract of JP 7-084879.
English language Abstract of JP 8-069417.
English language Abstract of JP 2000-200221.
U.S. Appl. No. 10/571,531 to Tanaka et al., filed Mar. 10, 2006.
U.S. Appl. No. 10/577,133 to Okabayashi et al., filed Apr. 10, 2006.
U.S. Appl. No. 10/578,314 to Tanaka et al., filed May 4, 2006.
U.S. Appl. No. 10/578,299 to Okabayashi et al., filed May 4, 2006.
Miyasaka Shuji
Nakanishi Ryuta
Okabayashi Hazuki
Tanaka Tetsuya
Ellis Kevin
Greenblum & Bernstein P.L.C.
Matsushita Electric - Industrial Co., Ltd.
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