Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-11-02
2009-06-30
Sough, Hyung S (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S142000, C711S133000, C711S134000, C711S135000, C711S136000
Reexamination Certificate
active
07555610
ABSTRACT:
The cache memory in the present invention includes a C flag setting unit40which adds, to each cache entry holding line data, a cleaning flag C indicating whether or not a write operation will be performed hereafter, and a cleaning unit39which writes back, to the memory, line data of a cache entry that has been added with a cleaning flag C indicating that a write operation will not be performed, and has been set with a dirty flag D indicating that the cache entry has been written into.
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Nakanishi Ryuta
Okabayashi Hazuki
Tanaka Tetsuya
Chery Mardochee
Greenblum & Bernstein P.L.C.
Panasonic Corporation
Sough Hyung S
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