Cache memory and control method thereof

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Details

C711S142000, C711S133000, C711S134000, C711S135000, C711S136000

Reexamination Certificate

active

07555610

ABSTRACT:
The cache memory in the present invention includes a C flag setting unit40which adds, to each cache entry holding line data, a cleaning flag C indicating whether or not a write operation will be performed hereafter, and a cleaning unit39which writes back, to the memory, line data of a cache entry that has been added with a cleaning flag C indicating that a write operation will not be performed, and has been set with a dirty flag D indicating that the cache entry has been written into.

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English Language Abstract of JP 61-016348.
English Language Abstract of JP 2001-005725.
English Language Abstract of JP 6-309231.
English Language Abstract of JP 9-259036.
English language Abstract of JP 10-293720.
English language Abstract of JP 2003-223360.
English language Abstract of JP 8-069417.
U.S. Appl. No. 10/571,531 to Tanaka et al., which was filed on Mar. 10, 2006.
U.S. Appl. No. 10/577,133 to Okabayashi et al., which was filed on Apr. 25, 2006.
U.S. Appl. No. 10/578,314 to Tanaka et al., which was filed on May 4, 2006.

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