Cache memory accessible for continuous data without tag...

Details Cache memory accessible for continuous data without tag... Cache memory accessible for continuous data without tag...

1998-09-04

2001-04-10

Yoo, Do (Department: 2185)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S118000, C711S128000, C707S793000

Reexamination Certificate

active

06216198

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a cache memory, and more particularly one for storing continuous data.
In a conventional cache memory, an address (tag) array is indexed (retrieved) for each access made from a processor to a cache memory and then making determination as to its registration (hit/miss-hit) in the cache memory. However, this conventional technology makes no classification of data registered in the cache memory and treats the data independently. Accordingly, no consideration is given to any relationship even if any relationship exists between data, and the determination of hit/miss-hit in the cache memory must be performed each time.
Some of the conventional cache memories pay particular attention to locality of address location of programs and operands executed by a processor. Thus, such a cache memory has employed a control system which retrieves, if data requested to be fetched by the processor hits the cache memory, a block next to the block thereof and pre-fetches, if the data miss-hits the cache memory, to a main storage unit.
However, the foregoing conventional technology is disadvantageous in that the necessity of hit/miss-hit determination carried out each time makes it difficult to perform high-speed accessing for reading continuous data.
SUMMARY OF THE INVENTION
In view of the foregoing problem of the conventional system, an object of the present invention is to provide a cache memory, which registers continuous data as such when the same is registered in the cache memory and thereby enables high-speed access to be made to the continuous data without retrieving a tag array when the same is read.
In a cache memory according to a first aspect of the present invention, the cache memory holds at least one of a forward and backward relationship between adjacent data included in continuous data.
With the unique and unobvious structure of the present invention, line numbers are provided without indexing a cache memory during accessing to continuous data.


REFERENCES:
patent: 5649144 (1997-07-01), Gostin et al.
patent: 5717916 (1998-02-01), Verma
patent: 5909704 (1999-06-01), Ireland

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