Cache memory

Details Cache memory Cache memory

2007-04-16

2010-10-26

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S133000, C711S167000, C711S173000, C711S207000

Reexamination Certificate

active

07822926

ABSTRACT:
A data processor includes a cache memory having a plurality of cache rows each row storing a cache line of data values, a memory management unit responsive to a page table entry to control access to a corresponding group of memory addresses forming a memory page, and a cache controller coupled to said cache memory and responsive to a cache miss to trigger a line fill operation to store data values into a cache row. The cache controller is responsive to a cache line size specifier associated with at least one page table entry to vary the number of data values within a cache line fetched in a line fill operation in dependence upon said cache line size specifier. Controlling cache line size on a page basis is more efficient than controlling cache line size on a cache row or virtual address basis.

REFERENCES:
patent: 5752275 (1998-05-01), Hammond
patent: 6349364 (2002-02-01), Kai et al.
patent: 2005/0240745 (2005-10-01), Iyer et al.
patent: 2007/0106871 (2007-05-01), O'Connor
Tang et al.,Cache with Adaptive Fetch Size, Technical Report ICS-00-16, Apr. 22, 2000, Department of Information and Computer Science, University of California, Irvine, 21 pages.
Tang et al,Adaptive Line Size Cache, Technical Report #-99-56, Nov. 1999, Department of Information and Computer Science, University of California, Irvine, 56 pages.

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