Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2002-05-13
2004-04-13
Phung, Anh (Department: 2824)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S154000
Reexamination Certificate
active
06721193
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the general field of cache memory circuits.
2. Description of the Related Art
Cache memory circuits are well known in the art as memory circuitry which may enable optimal response to the needs of a high speed processor. Cache memories are usable as temporary storage of information, for example of information relatively recently used by the processor. Information in cache RAM may be stored based upon two principles, namely spatial locality and temporal locality. The principle of spatial locality is based upon the fact that when data is accessed at an address, there is an above average likelihood that the data which is next required will have an address close to that of the data which has just been accessed. By contrast, temporal locality is based upon the fact that there is an above average probability that data which has just been accessed will be accessed again shortly.
In one approach therefore, when an item of data is accessed, adjacent data is written to cache memory in anticipation of the need to access it, and in another, the item which is accessed is stored. A desirable approach is to do both.
There are many different cache configurations, ranging from direct-mapped cache memory to fully-associative cache memory.
Although the present invention is described in the context of a set-associative cache memory, is not envisaged that it be so limited, and the architecture described and the particular circuit details are equally applicable to other types of cache.
In a typical cache memory, there is provided a so-called “tag memory” and a so-called “data memory”. Each entry in the tag memory has an associated entry in the data memory. The tag memory typically stores the most significant bits of an address at a position in the memory determined by the least significant bits of the address so that application of the least significant bits of the address to an address decoder causes the tag memory to output the stored most significant bits of an address. Comparison is then made between the output of the tag memory, namely the most significant bits of the stored address and the most significant bits of the address being sought. When identity occurs between the output of the tag memory and the address being sought, then there is said to be a hit in the tag memory. A line or entry in the data memory is associated with the access from the address decoder and a second output is made which consists of the data stored at an address. If there is a hit between the address applied to the cache and the tag information stored, then the contents of the data memory are output from the cache. If there is no hit, (this situation is termed a “miss”) then the contents of the data memory are not output.
According to the particular technique being used, a mechanism may exist for overwriting both the tag and data RAMs if no hit occurs.
It will be clear to those skilled in the art that timing difficulties exist in determining whether or not a hit has occurred, and in outputting the data from the data RAM upon the occurrence of a hit. For example, upon addressing a tag entry and the corresponding data entry, the tag information is output from the tag RAM and must then be compared with input address information and a decision reached as to whether or not identity exists. Only when the result of that decision has been validly determined can a gate be controlled to enable output of the data from the data RAM. The critical path is thus the tag RAM access.
A person skilled in the art will also be aware that memory sense amplifiers respond to differentials on bit lines or to potentials on bit lines to provide an output which corresponds to the information stored in the memory cells via bit lines, experience a delay after access to the memory cells of concern before those inputs have a sufficient potential difference to accurately sense the contents of the cell. This is due to the inherent capacitance and inductance of the bit lines. As a result, the sense amplifiers must be clocked at an instant which is sufficiently later than the memory cell access to ensure that the sense amplifier inputs are valid, and hence that the output of the sense amplifier will be valid. There is a further timing issue in that only at some interval after clocking of the sense amplifier-this interval being due to the inherent delay of the sense amplifier-the sense amplifier outputs will correspond to the memory cell contents. The outputs of the sense amplifier in a tag RAM typically form first inputs to a comparator, the comparator having second inputs formed by the most significant bits of the address concerned and further having an output fed to the above-mentioned gate. It will be appreciated by those skilled in the art that the comparator output should only indicate a hit when a tag hit is genuinely present or a miss when a tag miss is present. It is undesirable that the comparator output indicate a hit or miss merely because its inputs are not yet valid, because for example the sense amplifier providing those inputs has not yet settled or has not yet been enabled by the clock.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the invention there is provided a cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry and decision circuitry for selectively enabling said data RAM sense amplifier circuitry, said decision circuitry having a first input for stored tag data and a second input for address data, said decision circuitry having a first valid state when said tag data matches said address data and a second valid state different to said first valid state when said tag data differs from said address data, said decision circuitry having a control input for setting said decision circuitry to an invalid state different to said valid states, wherein said decision circuitry has first and second nodes, said nodes being at complementary logic levels in said valid output states and at a common potential in said invalid state.
Preferably said tag RAM sense amplifier circuitry has an enable input for receiving an enable signal, said cache memory further comprising timing circuitry having an input connected to said enable input and a first output connected to said control input of said decision circuitry, whereby said decision circuit attains one of said first and second valid states a first predetermined interval after application of an enable signal to said enable input of said tag RAM sense amplifier circuitry.
Advantageously said decision circuitry further comprises first current source circuitry for selectively applying a current to said first node when said address data differs from said stored tag data and second current source circuitry for applying a second current source to said second node and sensing circuitry having first and second sensing circuitry nodes, said sensing circuitry being responsive to a potential on said first and second nodes for establishing said first and second valid states on said first and second sensing circuitry nodes.
Conveniently said sensing circuitry comprises equalization circuitry responsive to said enable input of said tag RAM sense amplifier circuitry for selectively applying said common potential to said first and second sensing circuitry nodes.
Preferably, said sensing circuitry comprises a latch circuit connected between said first and second sensing circuitry nodes and selectively connectable to said first and second nodes via a gating circuit, said latch circuit and said gating circuit being activated by said control input.
Preferably again, said second current source circuitry is connected to a second output of said timing circuit, whereby said second current source is activated a second predetermined interval after said application of said enable signal. Conveniently, said first current source circuitry comprises a first transistor.
Advantageously, said tag RAM comprises a plurality of bit line pairs, each pair having an associated ta
Iannucci Robert
Phung Anh
Seed IP Law Group PLLC
STMicroelectronics Limited
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