Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2002-07-26
2004-04-13
Mai, Son (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C365S014000
Reexamination Certificate
active
06720663
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory circuits and, in particular, to integrated memory circuits.
BACKGROUND OF THE INVENTION AND PRIOR ART
Usually, integrated memory circuits are manufactured by providing a wafer, by subsequent processing of said wafer in order to produce the necessary doping structures and traces, and by finally dicing said wafer to obtain the individual memory chips. Then, the semiconductor memory chips are housed and shipped.
What is disadvantageous about the described procedure is the fact that, in particular during the manufacture of memory circuits, errors occur, which result in a memory chip having up to 30% of defective memory cells. After the memory manufacturer is informed about the typically expected error rate, e.g. a larger chip area than actually needed is used to obtain a one megabit memory chip in order to be able to compensate for the typically expected error rate by additional memory cells after manufacturing the memory. In a final functional test, the number of the defective memory cells will then be determined. If the number of defective memory cells may then be compensated by operational memory cells additionally present on the chip, a memory chip will pass the final quality control since the same has the specific value of for example one megabit.
What is disadvantageous about this procedure is the need to manufacture larger memory chips than actually needed right from the start in order to compensate for the post-productive defective memory cells. The chips are larger, meaning in other words, that less memory chips are obtained from one single wafer than if all memory cells were functional during memory manufacture and if for a one megabit memory chip only exactly the appropriate number of memory cells had to be manufactured. Here, it should be appreciated that a considerable share of the cost for the memory chips is not necessarily to be assigned to the development of memory chips but to the immense investment made by a semiconductor factory. If memory manufacture pays itself off or not rather depends on e.g. how many memory chips can be manufactured a day, provided that demand is accordingly great. Thus, as described above, if memory chips are provided with a larger design than actually needed, in order to compensate for unavoidable defects, the output in memory chips per wafer will decrease, which will have an immediate effect on the price of memory chips or even on profit and, thus, on the profitability for the memory manufacturer.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an inexpensive concept for the manufacture of integrated memory circuits as well as inexpensive integrated memory circuits.
In accordance with the present invention, this object is achieved by a method for manufacturing an integrated memory circuit, comprising the following steps: providing a semiconductor substrate having a front side and a rear side; processing the front side and the rear side of the semiconductor substrate to produce memory cells on the front side and to produce memory cells on the rear side of the semiconductor substrate; and replacing of defective memory cells on one side of the semiconductor substrate by operational memory cells on the other side of the semiconductor substrate by connecting the operational memory cells on the other side of the semiconductor substrate to an input/output circuit of the memory circuit.
The present invention is based on the finding that yield may be considerably increased by no longer processing the semiconductor wafer on one side, as in the state of the art, but by providing both sides of the wafer with memory circuits. An inventive integrated memory circuit does not only have memory cells and conductive traces on one side but is also provided with memory cells and conductive traces on the other.
An advantage of the present invention is that, as compared to the state of the art, it is possible to double the number of memory cells per chip area.
Assuming that memory cell defects are randomly distributed, the simultaneous occurrence of errors on both sides of the memory chip is considerably lower, since probabilities, which are typically values of much less than one, multiply themselves, which results in a total error probability which is much less than the probability of one side of the wafer being defective. Here, the error probability may also be construed such that a memory chip may be classified as defective due to a number of memory cells which is too large in total, i.e. that the memory chip itself will not pass the final quality control.
One further advantage of the present invention is that the chip area of a memory chip does not need to be made larger than actually required due to defects made during the manufacture, but that it may even be reduced significantly since the inventive integrated memory circuit comprises memory cells on both sides.
REFERENCES:
patent: 5313097 (1994-05-01), Haj-Ali-Ahmadi et al.
patent: 6215699 (2001-04-01), Yamamoto
patent: 6462995 (2002-10-01), Urakawa
patent: 39 14 055 (1990-10-01), None
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