Cache memories using DRAM cells with high-speed data path

Details Cache memories using DRAM cells with high-speed data path Cache memories using DRAM cells with high-speed data path

1999-04-14

2001-03-13

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S230020, C711S113000

Reexamination Certificate

active

06201740

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to cache memory devices and in particular the present invention relates to a DRAM cache memory device.
BACKGROUND OF THE INVENTION
The performance of computer systems, especially personal computers, has improved dramatically due to the rapid growth in computer architecture design and in particular to the performance of computer memory.
Computer processors and memories, however, have not pursued the same pace of development through the years. Memories are not able to deliver enough response speed to processors. To reduce the gap in speed between the processors and memories, the concept of memory hierarchy was introduced. A memory hierarchy comprises a number of different memory levels, sizes and speeds. The memory located near or inside the processor is usually the smallest and fastest and is commonly referred to as cache memory. Cache memory plays an important role in the computer memory hierarchy. Computer instructions and data which are most likely to be reused are stored temporarily in the cache memory, because the processor can access these instructions or data much faster than accessing them from the slower computer main memory. Cache memory needs to be fast to accommodate the demand of the processor, therefore it is usually constructed from static-type memory or static random access memory (SRAM). SRAM's, however, do not have the memory density of comparable dynamic memories. For an example of an SRAM and additional background in the terminology and specifications for an SRAM, see 1995/1996 SRAM DATA BOOK, pages 1-145 to 1-159, provided by Micron Technology, Inc., the assignee of the present invention, which is incorporated herein by reference.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a dynamic random access memory (DRAM) which can be used for cache memory.
SUMMARY OF THE INVENTION
The above mentioned problems with cache memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A DRAM memory is described which uses multiplexed global bit lines and latch circuits to communicate data with I/O lines. The DRAM operates as a synchronous pipelined memory.
In particular, the present invention describes a dynamic memory device comprising dynamic memory cells, global bit line pairs coupled to the memory cells, and addressing circuitry to electrically connect the global bit line pairs to latch circuits, the latch circuits each having a write circuit. The write circuit comprising a coupling circuit for selectively coupling the latch circuits to an input/output connection, a data latch circuit connected to the coupling circuit, and input data driver circuits coupled to one of the bit line pairs and the data latch circuit. The memory further comprises a multiplex circuit connected between the latch circuits and an input/output connection for coupling one of the latch circuits to the input/output connection.
In another embodiment, a dynamic memory device is described which comprises dynamic memory cells, global bit line pairs coupled to the memory cells, and addressing circuitry to electrically connect the global bit line pairs to latch circuits, the latch circuits each having a read circuit. The read circuit comprises first and second inputs connected to the global bit lines, a data latch circuit selectively coupled to the first and second inputs through electrical isolation circuitry, and driver circuitry connected to first and second outputs. The memory further comprises a multiplex circuit connected between the latch circuits and an input/output connection for coupling one of the latch circuits to the input/output connection.


REFERENCES:
patent: 4303986 (1981-12-01), Lans
patent: 5666312 (1997-09-01), Robertson
patent: 5831924 (1998-11-01), Nitta et al.
patent: 6006309 (1999-12-01), Shelly et al.

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