Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-10-10
2006-10-10
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07120749
ABSTRACT:
According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.
REFERENCES:
patent: 6668306 (2003-12-01), Rakvic et al.
patent: 6865736 (2005-03-01), Holmberg et al.
patent: 2001/0021959 (2001-09-01), Holmberg et al.
PCT Search Report, PCT/US2005/008337, mailed Jul. 13, 2005.
Black Bryan
Rakvic Ryan
Shen John
Wu Youfeng
Blakely, Sokoff, Taylor & Zafman LLP
Ellis Kevin L.
Intel Corporation
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