Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-06-14
2011-06-14
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S130000, C711S141000, C711SE12045
Reexamination Certificate
active
07962693
ABSTRACT:
A cache management system providing improved page latching methodology. A method providing access to data in a multi-threaded computing system comprises: providing a cache containing data pages and a mapping to pages in memory of the multi-threaded computing system; associating a latch with each page in cache to regulate access, the latch allowing multiple threads to share access to the page for reads and a single thread to obtain exclusive access to the page for writes; in response to a request from a first thread to read a particular page, determining whether the particular page is in cache without acquiring any synchronization object regulating access and without blocking access by other threads; if the particular page is in cache, reading the particular page unless another thread has exclusively latched the particular page; and otherwise, if the particular page is not in cache, bringing the page into cache.
REFERENCES:
patent: 5483596 (1996-01-01), Rosenow et al.
patent: 2004/0128470 (2004-07-01), Hetzler et al.
Bragdon Reginald G
iAnywhere Solutions, Inc.
Sterne Kessler Goldstein & Fox PLLC
Vo Thanh D
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