Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-08-02
2010-11-02
Song, Jasmine (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S143000, C711S144000, C711S163000
Reexamination Certificate
active
07827360
ABSTRACT:
A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line.
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International Search Report for corresponding PCT Application No. PCT/US2008/067225, mailed Feb. 19, 2009.
Bruce Klas M.
Greenberg David F.
Rahman Syed R.
Smittle Matt B.
Snyder Michael D.
Freescale Semiconductor Inc.
Song Jasmine
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