Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-07-08
2008-07-08
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S135000, C711S136000, C711S159000
Reexamination Certificate
active
07398357
ABSTRACT:
Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed. The cache additionally comprises MFU circuitry (1) adapted to produce new state information for the at least two given cache lines in response to an access to one of the at least two given cache lines, and (2) when a cache miss occurs in one of the at least two given cache lines, adapted to determine, based on the new state information, which of the at least two given cache lines is the most frequently used cache line.
REFERENCES:
patent: 5937429 (1999-08-01), Kumar et al.
patent: 6883066 (2005-04-01), Herbst et al.
patent: 2002/0194432 (2002-12-01), Rodriguez
patent: 2005/0015555 (2005-01-01), Wilkerson
Matick Richard Edward
Moreno Jaime H.
Ware Malcolm Scott
International Business Machines - Corporation
Kim Matt
Patel Hetul
Ryan & Mason & Lewis, LLP
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