Cache line purge and update instruction

Details Cache line purge and update instruction Cache line purge and update instruction

2006-05-16

2006-05-16

Padmanabhan, Mano (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S135000, C711S143000, C711S155000, C711S163000

Reexamination Certificate

active

07047365

ABSTRACT:
A method and apparatus for purging a cache line from an issuing processor and sending the cache line to the cache of one or more processors in a multi-processor shared memory computer system. The method and apparatus enables cache line data to be moved from one processor to another before the receiving processor needs the data thus preventing the receiving processor from incurring a cache miss event.

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IBM Technical Disclosure Bulletin, Purging Shared Cache lines in a MUlti-Processor Node, Nov. 1993, IBM, vol. 36, pp. 1-6.

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