Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-07-11
2006-07-11
Peikari, B. James (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S121000, C711S124000, C711S142000, C711S143000, C711S144000, C711S128000, C711S137000, C711S147000, C711S205000, C711S206000
Reexamination Certificate
active
07076613
ABSTRACT:
The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.
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Lai Konrad
Peir Jih-Kwon
Robinson Scott H.
Wang Wen-Hann
Zhang Steve Y.
Intel Corporation
Li Zhuo H.
Peikari B. James
Schwegman Lundberg Woessner & Kluth P.A.
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