Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-07-12
2011-07-12
Verbrugge, Kevin (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S165000, C711SE12018, C711SE12061
Reexamination Certificate
active
07979640
ABSTRACT:
Embodiments of the present invention provide a system that handles way mispredictions in a multi-way cache. The system starts by receiving requests to access cache lines in the multi-way cache. For each request, the system makes a prediction of a way in which the cache line resides based on a corresponding entry in the way prediction table. The system then checks for the presence of the cache line in the predicted way. Upon determining that the cache line is not present in the predicted way, but is present in a different way, and hence the way was mispredicted, the system increments a corresponding record in a conflict detection table. Upon detecting that a record in the conflict detection table indicates that a number of mispredictions equals a predetermined value, the system copies the corresponding cache line from the way where the cache line actually resides into the predicted way.
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Spjuth, Mathias, et al., “The Elbow Cache: A Power-Efficient Alternative to Highly Associative Caches”, Technical report 2003-046, Department of Information Technology, Uppsala University, http://www.it.uu.se/research/reports/2003-046/2003-046-nc.ps, 2003.
Spjuth, Mathias, et al., “Low-Power and Conflict Tolerant Cache Design”, Technical report 2004-024, Department of Information Technology, Uppsala University, http://www.it.uu.se/research/publications/reports/2004-024/, 2004.
Chaudhry Shailender
Cypher Robert E.
Karlsson Martin
Jones Anthony
Oracle America Inc.
Park Vaughan Fleming & Dowler LLP
Verbrugge Kevin
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