Cache invalidation bus for a highly scalable shared cache...

Details Cache invalidation bus for a highly scalable shared cache... Cache invalidation bus for a highly scalable shared cache...

2002-08-08

2004-11-30

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S122000

Reexamination Certificate

active

06826654

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a data processing system in general, and in particular to a data processing system having a cache memory hierarchy. Still more particularly, the present invention relates to a data processing system having a highly scalable shared cache memory hierarchy.
2. Description of the Related Art
Broadly speaking, all processing units within a symmetric multiprocessor (SMP) data processing system are generally identical. In other words, all of the processing units within an SMP data processing system generally have the same architecture and utilize a common set or subset of instructions and protocols to operate. Each processing unit within the SMP data processing system includes a processor core having multiple registers and execution units for carrying out program instructions. The SMP data processing system may also include a cache memory hierarchy.
A cache memory hierarchy is a cache memory system consisting of several levels of cache memories, each level having a different size and speed. Typically, the first level cache memory, commonly known as the level one (L1) cache, has the fastest access time and the highest cost per bit. The remaining levels of cache memories, such as level two (L2) caches, level three (L3) caches, etc., have a relatively slower access time, but also a relatively lower cost per bit. It is quite common that each lower cache memory level has a progressively slower access time and a larger size.
Within a cache memory hierarchy, when multiple L1 caches share a single L2 cache, the L2 cache is typically inclusive of all the L1 caches. In other words, the L2 cache has to maintain an inclusivity bit per L1 cache line in an L2 directory. Consequently, the L2 directory, which is a costly resource, grows substantially as the total number of L1 cache lines increases. As a result, the additional inclusivity bit information in the L2 directory leads to a relatively large L2 cache design with slower access time to the L2 directory. Also, when the L2 cache needs to cast out a cache line, for example, to make spaces, the L2 cache must invalidate the associated cache line in the L1 cache because the L2 cache cannot track the inclusivity of that cache line anymore. However, the information in the L1 cache line that had been “involuntarily” casted out from the L1 cache may still be useful to the corresponding processor. The present disclosure provides a solution to the above-mentioned problems.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units includes a level one cache memory. All the level one cache memories are associated with a level two cache memory. The level two cache memory is non-inclusive of all the level one cache memories. An invalidation bus is connected to all of the level one cache memories. In response to a write access to a specific cache line within one of the level one cache memories, the invalidation bus invalidates other cache lines that shared identical information with the specific cache line within the rest of the level one cache memories.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 2002/0152359 (2002-10-01), Chaudhry et al.
The Authoritative Dictionary of IEEE Standards Terms, 2000, IEEE Press, Seventh Edition, pp. 266 and 712.

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