Cache intervention on a separate data bus when on-chip bus...

Details Cache intervention on a separate data bus when on-chip bus... Cache intervention on a separate data bus when on-chip bus...

2011-08-09

2011-08-09

Peugh, Brian R (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S124000, C711S119000, C710S027000, C710S110000

Reexamination Certificate

active

07996614

ABSTRACT:
Computer implemented method, system and computer usable program code for processing a data request in a data processing system. A read command requesting data is received from a requesting master device. It is determined whether a cache of a processor can provide the requested data. Responsive to a determination that a cache of a processor can provide the requested data, the requested data is routed to the requesting master device on an intervention data bus of the processor separate from a read data bus and a write data bus of the processor.

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