Cache holding register for receiving instruction packets and for

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711 3, 711118, 711119, 711130, 711137, 711149, 711154, 711167, 712 1, 712200, 712207, G06F 1200, G06F 1300

Patent

active

059833211

ABSTRACT:
An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register. In order to reduce the number of ports employed upon the instruction bytes storage used to store cache lines of instructions, the cache holding register retains the cache line until an idle cycle occurs in the instruction bytes storage. The same port ordinarily used for fetching instructions is then used to store the cache line into the instruction bytes storage. In one embodiment, the instruction cache prefetches a succeeding cache line to the cache line which misses. A second cache holding register is employed for storing the prefetched cache line.

REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5148537 (1992-09-01), Belsan
patent: 5170476 (1992-12-01), Laakso et al.
patent: 5179680 (1993-01-01), Colwell et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5301295 (1994-04-01), Leary et al.
patent: 5450561 (1995-09-01), Ryan
patent: 5454093 (1995-09-01), Abdulhafiz et al.
patent: 5465344 (1995-11-01), Hirai et al.
patent: 5511178 (1996-04-01), Takeda et al.
patent: 5623615 (1997-04-01), Salem et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5689672 (1997-11-01), Witt et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," 1994, pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.

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