Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-02-17
2004-03-30
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S128000, C711S130000, C711S145000
Reexamination Certificate
active
06715035
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to processing systems and more particularly to a system and method for reducing the effective latency of memory transfer.
BACKGROUND OF THE INVENTION
Memory technology is constantly focused on increasing the speed of the transfer of data from the computer memory to the processor. A specific problem that memory technology is faced with concerns first transfer latency. First transfer latency is the time it takes the first piece of data to be returned to a processor once the data is requested from main memory. Because of first transfer latency, a processor must sometimes wait an inordinate amount of time to retrieve data from the memory of the computer system.
Currently the solution to this problem is the use of internal and external processor caches. The cache fetches the data that the processor is requesting plus other data which the processor may request and stores the data in its storage elements. Should a processor request data that is currently in the cache (a cache hit), first transfer latency of the processor is less than if the processor accesses data from main memory. If the data that is requested is not in the cache (a cache miss), the processor has to access the data from memory and incur a first transfer latency delay.
Currently, large external caches on the order of 16 megabytes are implemented to increase the number of cache hits. However, even with the larger caches currently being used, because of the speed difference between the processor and the main memory, the processor can spend 50% of its time simply waiting for data from the main memory. Also, to have the necessary speed to handle the data, these caches must be assembled in a way that may become cost prohibitive. Moreover, the larger the cache the more power it consumes.
Accordingly, what is needed is a system and method for reducing the first transfer latency of a computer processor in order to enable the processor to run more effectively. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A cache for use in a memory controller, which processes data in a computer system having at least one processor, is disclosed. The cache comprises a tag array comprising a plurality of tag entries, wherein each of the plurality of tag entries comprises a tag, at least one least recently used bit, and a pointer. The cache also comprises a data array comprising a plurality of data entries, wherein the pointer points to one of the plurality of data entries, wherein the number of times the at least one processor must undergo a first transfer latency is reduced.
Through the use of a memory controller device in accordance with the present invention, the number of times that a processor must undergo full first transfer latency is reduced. This is done by incorporating a prefetch mechanism within a small cache. By reducing the number of times that a processor must undergo full first transfer latency, computer processors will be able to operate more efficiently. Also, a system and method in accordance with the present invention can be used in both single processor and multi-processor systems.
REFERENCES:
patent: 6098150 (2000-08-01), Brethour et al.
Colglazier Daniel J.
Dombrowski Chris
Genduso Thomas B.
Gossage Glenn
McKinley Martin
Sawyer Law Group
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