Electrical computers and digital processing systems: processing – Processing control
Reexamination Certificate
2007-03-20
2007-03-20
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
C712S207000
Reexamination Certificate
active
10628083
ABSTRACT:
A method for compressing a set of instructions in an adaptive computing machine includes identifying frequently executed instructions, inserting an explicit caching instruction associating the identified instructions with an index value in the set of instructions before the identified instructions and replacing at least one instance of the frequently executed instructions subsequent to the explicit caching instruction with a compressed instruction referencing the index value. One or more instructions can be identified for compression, including groups of consecutive or non-consecutive instructions. The explicit caching instruction directs a node in an adaptive computing machine to store instructions in an instruction storage unit in association with an index value. Instructions stored in the storage unit are retrievable with reference to the index value. The compressed instruction may include one or more references to index values, and can include a sequence of index values indicating the sequence of execution of the associated instructions.
REFERENCES:
patent: 4713755 (1987-12-01), Worley et al.
patent: 5534796 (1996-07-01), Edwards
patent: 5694613 (1997-12-01), Suzuki
patent: 5704053 (1997-12-01), Santhanam
patent: 5734808 (1998-03-01), Takeda
patent: 5835753 (1998-11-01), Witt
patent: 6154494 (2000-11-01), Araki et al.
patent: 6601158 (2003-07-01), Abbott et al.
patent: 6615333 (2003-09-01), Hoogerbrugge et al.
patent: 6684319 (2004-01-01), Mohamed et al.
patent: 6721884 (2004-04-01), De Oliveira Kastrup Pereira et al.
patent: 6819140 (2004-11-01), Yamanaka et al.
patent: 6823448 (2004-11-01), Roth et al.
patent: 6865664 (2005-03-01), Budrovic et al.
patent: 6883074 (2005-04-01), Donohoe
patent: 6907598 (2005-06-01), Fraser
patent: 2001/0029515 (2001-10-01), Mirsky
patent: 2004/0133745 (2004-07-01), Ramchandran
patent: 2004/0168044 (2004-08-01), Ramchandran
patent: 2005/0166037 (2005-07-01), Barrick
Coleman Eric
NVIDIA Corporation
Patterson & Sheridan L.L.P.
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