Cache for instruction set architecture

Details Cache for instruction set architecture Cache for instruction set architecture

2003-07-24

2008-03-04

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S003000, C711S119000, C711S131000, C711S218000

Reexamination Certificate

active

07340562

ABSTRACT:
A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number of data address generators are connected with a memory unit and the data buses. The data address generators retrieve data values from the memory unit and communicate the data values to the data buses without latency. The data address generators are adapted to simultaneously communicate each of the data values to a different data bus without latency. The cache memory units are adapted to simultaneously load data values from the data buses, with each data value loaded into a different cache line without latency.

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Computer Organization and Design 2ndEdition, Hennessy, 1998, Morgan Kaufmann Publishers, pp. 569-570.

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