Cache-flushing engine for distributed shared memory...

Details Cache-flushing engine for distributed shared memory... Cache-flushing engine for distributed shared memory...

2005-03-29

2005-03-29

Padmanabkan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S141000, C711S147000

Reexamination Certificate

active

06874065

ABSTRACT:
A cache coherent distributed shared memory multi-processor computer system is provided with a cache-flushing engine which allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the cache-flushing engine, a “flush” command is issued which forces the owner cache to write-back the dirty cache line to be flushed. Subsequently, a “flush request” is issued to the home memory of the memory block. The home node will acknowledge when the home memory is successfully updated. The cache-flushing engine operation will be interrupted when all flush requests are complete.

REFERENCES:
patent: 5432918 (1995-07-01), Stamm
patent: 6021473 (2000-02-01), Davis et al.
patent: 6049857 (2000-04-01), Watkins
patent: 6105112 (2000-08-01), Arimilli et al.
“Computer Organization and Design”, Second Edition, Edited by John L. Hennessy & David A. Patterson publish in 1998 by Morgan Kaufmann Publisher, Inc. p. 614-615.

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