Cache flushing

Details Cache flushing Cache flushing

1999-12-15

2003-12-02

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

06658532

ABSTRACT:

BACKGROUND
This invention relates to cache flushing.
A cache is flushed in order to make sure that the contents of the cache and a main memory are the same. Typically, a cache flush is initiated by a processor issuing a flush command. A cache controller will then write back data from the cache into the main memory.
SUMMARY OF THE INVENTION
Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.


REFERENCES:
patent: 5745730 (1998-04-01), Nozue et al.
patent: 5845326 (1998-12-01), Hirayama et al.
patent: 6003116 (1999-12-01), Morita et al.

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