Cache flush system and method thereof

Details Cache flush system and method thereof Cache flush system and method thereof

2007-01-30

2007-01-30

Peikari, B. James (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000, C711S146000, C711S133000, C707S793000

Reexamination Certificate

active

10731019

ABSTRACT:
The present invention relates to a cache flush system and the method for a cache flush performed in cache memory against at least one corresponding prescribed event in a multi-processor system. Embodiments of the present invention can reduce or minimize loads of a processor bus by performing memory read of at most a prescribed size and can increase simultaneousness of cache flush against a corresponding prescribed event by performing a cache flush directly triggered by the prescribed event thereby enabling high speed and automated cache flush algorithm.

REFERENCES:
patent: 5835949 (1998-11-01), Quattromani et al.
patent: 6230151 (2001-05-01), Agrawal et al.
patent: 6418515 (2002-07-01), Kurosawa
patent: 6976128 (2005-12-01), Williams et al.
patent: 2003/0009631 (2003-01-01), Arimilli et al.
patent: 2004/0133562 (2004-07-01), Toong et al.

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