Cache flush request circuit flushes the cache if input/output sp

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3642383, 3642397, 364240, 364262, 3642681, 36424341, 36492692, 364933, 3649666, 3649354, 364DIG1, 364DIG2, G06F 1206, G06F 1300

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050954288

ABSTRACT:
A computer system which flushes the cache controller when a circuit board is being configured or is responding to an input/output write operation. The flush operation can be disabled for each circuit board location. A cache flush operation can also be directly requested.

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G. Laws, "Multiprocessing on the Nubus Using Cache Inhibited Pages," Microprocessors & Microsystems, vol. 12, No. 3, pp. 147-152. (Apr. 1988).
W. Van Loo, "Maximize Performance by Choosing Best Memory," Computer Design, vol. 26, No. 14, pp. 89-94 (Aug. 1987).
IBM Personal System/2 Model 80 Technical Reference Manual, 1987, pp. 2-8 to 2-14 and 2-29 to 2-51.
Intel Corporation, Microprocessor and Peripheral Handbook, vol. 1, 1988, pp. 4-287 to 4-348.

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