Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-02-17
1999-06-15
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711134, G06F 1212
Patent
active
059132256
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a mechanism for cache flushing hardware for PCs having secondary cache. Particularly, this mechanism is well applicable to a system having plurality of modes, using plurality of address system for the memory location.
BACKGROUND
A CPU has a signal input named FLUSH# for flushing the internal cache system. The FLUSH# signal, when it is driven low by the system core, which controls and manages accessing to the memory, the CPU is forced to flush the entire contents of the on-chip cache. The CPU system is usually made up of a few components other than the CPU itself, for example, a main memory to store information and being accessed by the CPU to derive the data stored therein, a first cache memory which resides between the CPU and the main memory and provides a relatively very fast access to a required data and storing a flick portion of data which is occasionally accessed by the CPU and is duplicatedly stored in the main memory, and preferably a second cache which resides between the first cache memory and the main memory, which is not as fast as the first cache memory, but has an ability to store more data. The second cache memory also has a signal input line named FLUSH#, having similar purpose and function.
There are two ways for data write handling between the CPU and the secondary cache. One is write-through operation, which writes data to secondary cache and the main memory at the same time even if the CPU wanted the data to be written only into the secondary cache. The other is write-back operation, which only writes the data to the secondary cache when the CPU wanted the data to be written only into the secondary cache. In other words, there will be no back-up data in main memory in the case of write-back operation. As is easily imagined, the write-back operation is more efficient in view of data transfer, but it has a disadvantage that the contents of the secondary cache have to be transferred or "write-back" to the main memory at the occasion of cache flush for back-up purpose.
These components of the system are being connected by a common data transfer line called a CPU bus. Since the bus is common to all the components of the system, an access conflict may occur in the case of starting write-back cycles in response to FLUSH# signal. Therefore, an arbitration mechanism is needed to avoid this conflict. Before writing back the modified lines, the secondary cache must obtain ownership of the CPU bus in order to start write back cycle.
The CPU system typically mentioned herewith is shown in FIG. 1. In this figure, the first cache is included within the CPU and is not shown. The main memory is supposed to be connected to the secondary cache, but it is also not shown. The secondary cache is connected to both of the CPU and the system core by FLUSH#. The system core is a component which controls the input/output operation between the CPU, the secondary cache and the main memory. The FLUSH# provides the request to flush the first and secondary cache from the system core to the CPU. The CPU and the system core is connected via HOLD and HLDA. The HOLD is driven when the system core requests the CPU to release the bus. In turn, the CPU releases the bus after it has finished with the current tasks using bus, asserts HLDA# through HLDA to inform of the fact that the bus has been released. However, the secondary cache cannot obtain the ownership of the bus by itself in this system, since it can not transfer a signal to obtain the bus to the CPU nor the system core. This results into a conclusion that write-back operation can not be achieved in this system, because in order to achieve write-back operation, the secondary cache has to intensively obtain the ownership of the bus prior to starting write-back cycles.
This is the primary problem in the prior art. To solve this problem, BOFF# lines is added to the system. This line connects the secondary cache to the CPU, and when this is asserted, the CPU will instantly release the bus line, in turn the secondary c
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patent: 5638532 (1997-06-01), Frame et al.
Nakada Takeo
Ohba Nobuyuki
Chan Eddie P.
International Business Machines - Corporation
Magistrale Anthony N.
McConnell Daniel E.
Portka Gary J.
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