Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-12-26
2006-12-26
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000
Reexamination Certificate
active
07155573
ABSTRACT:
A method for estimating the fall through time of a cache includes maintaining local statistics associated with each data cache slot replaced by a processor, reading from a memory global statistics related to each data cache slot replaced by a plurality of processors, calculating new global statistics, and estimating a fall through time of the cache in response to the global statistics at a predetermined rate. When the global statistics are the result of at least a threshold number of data cache slots having been replaced, the new global statistics are calculated by weighting the global statistics by a factor of less than one and adding the weighted global statistics to the local statistics. When the global statistics are not the result of at least a threshold number of data cache slots having been replaced, the new global statistics are calculated by adding a time related to the lapsed time to a global sum value associated with the time stamp difference of the replaced data cache slots. In a multi-processor computer system, each of the processors accesses the global memory to update the global statistics at a different time. The fall through time is estimated continuously at a first predetermined rate and the global statistics are updated at a second predetermined rate that, in one embodiment, is a multiple of the first predetermined rate.
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Ezra Josef
Levin-Michael Orit
Daly, Crowley, Mofford and Durkee, LLP
EMC Corporation
Nguyen Hiep T.
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