Cache eviction technique for reducing cache eviction traffic

Details Cache eviction technique for reducing cache eviction traffic Cache eviction technique for reducing cache eviction traffic

2007-10-02

2007-10-02

Lane, Jack (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S122000, C711S133000, C711S134000, C711S144000, C711S145000

Reexamination Certificate

active

11087916

ABSTRACT:
A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.

REFERENCES:
patent: 5584013 (1996-12-01), Cheong et al.
patent: 6195729 (2001-02-01), Arimilli et al.
patent: 6601143 (2003-07-01), Lamparter
patent: 2006/0155934 (2006-07-01), Rajamony et al.

Affiliated with

Also associated with

Rating

Cache eviction technique for reducing cache eviction traffic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache eviction technique for reducing cache eviction traffic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache eviction technique for reducing cache eviction traffic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3900829